As 16 Megabit DRAM devices move toward production, the requirements placed on dielectric films used for inter-metal isolation exceed the capabilities of traditional films and techniques. First-level metal spaces as small as 0.5 micron and metal thickness as great as 0.9 micron are encountered. For these dimensions standard deposition techniques such as plasma TEOS CVD (PETEOS) result in voids or sharply cusped seams between the leads.
These issues can be addressed by the use of spin-on glasses (SOG), but these films tend to crack and absorb and release water vapor and other gases, which interfere with subsequent processing. Therefore, blanket etchback is often used to remove the SOG from the vicinity of vias. Achieving good planarization using SOG techniques generally requires multiple coat/cure cycles and the surface planarity is generally degraded by the plasma loading effects during etchback. Sequential depositions and etchbacks of TEOS oxides can provide filling of submicron gaps and a smoothed surface profile. This approach is generally effective only for gaps greater than 0.7 micron. The degree of planarity required over widely spaced metal lines for 16 Megabit devices is rather difficult to achieve using such prior techniques.
Similarly stringent requirements have also emerged for the protective over coat dielectric. Inter-lead capacitance becomes a limiting factor in device speed and performance, thus the leads need to be isolated by a material having a lower dielectric constant than traditional plasma nitride film. Secondly, a smaller cross section of the metal leads increases their susceptibility to mechanical displacement or rupture from forces created during the packaging process. This, as well as the advent of the Lead Over Chip (LOC) packages in which the top of the chip is taped to the bottom of the lead frame makes smoothing of the top chip surface very desirable.